Samsung Science & Technology Center

Although various synapse devices have been studied for the past 10 years, none of them were able to meet all the key requirements for universal HNN applications. Since the requirements such as retention, operation speed, multi-level conductance, and low-power operation conflict with each other, it is difficult to implement a highly integrated nanoscale synapse device.

In this presentation, we summarize the limitations of the synapse devices reported by various groups so far and suggest possible future research directions. Even though universal synapse devices cannot be implemented yet, we would like to discuss applications of the synapse devices developed so far in specialized AI HW systems (i.e. inference only, on-chip training).

Recently, a lot of synaptic devices with stable multi-states have been demonstrated for neuromorphic applications. However, the implementation of neuromorphic system with multiple weights requires severe circuit overhead and it has been considered as one of serious challenges on the way to commercialization. To solve this problem, binary neural network (BNN) accelerator-based Processing-In-Memory (PIM) architecture using emerging nonvolatile memory has attracted significant attention owing to its simplicity. Among them, FeFET BNN have been intensively researched owing to its promising attributes of nonvolatility, fast operation speeds, small footprints, and large computational power saving. Despite its advantages, BNN poses a concern of low classification accuracy such that this motivates a need for improving the classification accuracy of FeFET-based PIM system [1]. Thus, to enhance the deep learning classification accuracy without area penalty, we propose area-efficient 2T FeFET Ternary Neural Network (TNN) array for PIM applications [2]. In the proposed architecture, ternary multiplication operation is performed by comparing input data with the weights stored in series-connected two FeFETs which can hold binary states. Through TNN array simulations including peripheral circuits, the feasibility of the proposed ternary operation is verified by the outputs with stable ternary states. Furthermore, the classification accuracy of 87.89% on CIFAR-10 dataset is achieved by utilizing fully discretized VGG-big model.

Artificial intelligence (AI) will enable machines to think and solve complex tasks like human beings. In recent years, artificial neural networks have improved recognition and classification accuracy. However, state-of-theart deep learning algorithms require large network models with multiple layers, which pose significant challenges for complementary metal-oxidesemiconductor (CMOS) implementation due to limitations in conjoining computation, memory, and communication requirements in large networks. As an alternative hardware platform, resistive devices (memristors) have been proposed for weight storage and fast parallel neural computing with low power consumption. The parallelism property of the resistive crossbar arrays for matrix-vector multiplication enables significant acceleration of core neural computations. In this talk, Prof. Choi will talk about the approaches how to achieve highly reliable artificial neurons and synapses for neuromorphic computing which can be a key step paving the way towards post von Neumann computing. Finally, he will discuss the projections and future directions of the memristor-based system.

Artificial synaptic devices are essential elements in brain-inspired neuromorphic computing systems. The artificial synapses in neuromorphic systems should perform signal processing and consequent updating of their synaptic weight for learning and memory operations, which alleviates the delay issues in data-transfer that occur in von Neumann systems. To date, various synaptic devices have been investigated by employing two-terminal memristors and three-terminal transistors having conductance (or resistance) modulation. However, it is still challenging to realize artificial synapses with high performance and reliability for practical applications. In particular, due to the inherent random nature of resistance changing characteristics, it is difficult to design synaptic properties for specific neural networks. In this talk, the challenges in two-terminal and three-terminal resistive changing synaptic devices will be discussed to achieve high performance, reliability, and designability of synaptic characteristics for neuromorphic computing applications.

With an expectation of achieving a brain-like efficiency and large performance gain, there has been increasing interest in mapping artificial neural networks into cross-point arrays of novel non-volatile memory devices. Such cross-point array architectures based on resistive memory devices, which can be operated in an analog and massively parallel manner, have shown potential to achieve a large acceleration in computation for artificial intelligence (AI). For realization of such architectures in hardware, the specifications for synaptic devices are revealed to be different in many aspects with those for traditional memory devices, necessitating new material systems and device designs as well as novel algorithms and architectures for efficient AI computation. In this talk, I will share the key issues and roadblocks which prevent analog neural network training accelerators from being realized today, and discuss the research directions to improve the system performance using non-ideal devices.

Memristor crossbars have been studied for many years in order to develop new backpropagation acceleration hardware, which is a key algorithm in training neural networks. However, the hardware implementation of deeplearning accelerators using memristors necessitates the use of ADC and DAC circuits, which consume a lot of power. Another issue for training neural networks on memristor crossbars is the limited precision of memristor programming. Furthermore, the complicated mathematical process of the backpropagation algorithm, which requires extensive computation, makes on-line or in-situ training of memristor crossbars extremely difficult. All of the aforementioned factors make memristor crossbars suitable only for inference operation and not for training, which should be performed by traditional digital circuits such as GPU and NPU rather than memristor crossbars. To avoid the problems described above with memristor crossbars for backpropagation, an alternative method of training that does not rely on backpropagation is required. To that end, we reviewed the hardware solution of the equilibrium propagation algorithm, which is one of the energy-based models that can train neural networks not using the backpropagation, in this talk. We consider some issues with the hardware implementation of the equilibrium propagation algorithm and discuss potential research directions.

Analog synaptic device is a very popular topic among device researchers. We do have more than enough papers being published in high-impactfactor journals, which might contribute to the success of the field in the long run. However, the history of artificial intelligence tells us that overinflated promises without real-world applications or meaningful progresses is a perfect recipe for long winter. In this talk, I would like to share my early thoughts on how we can prevent or slow down the winter from coming by addressing some of these questions - Are we making enough progresses? What will be killer apps for AiMC (Analog in-Memory Computing)? Any opportunities for a device/algorithm co-design?

Since the ‘neuromorphic’ was suggested as a key direction that promises the disruptive innovation in the next-generation computing platform, there has been extensive research on fusing brain-inspired concepts into the designs of new devices and circuits. Struggling throughout the past decades in building reliable commercial products results in compromising its scope and focusing on the edge AI with an energy-efficient processing in a crossbar memory array. In the meantime, the DNN model continues evolutions from CNN to EfficientNets and Transformers which consist of multiple blocks of various layers with very different layer-by-layer characteristics in required memory bandwidth, precision and activation functions. It presents a potential threat of losing the chances from the ever-increasing gap between the architecturelevel considerations and what could be provided by the neuromorphic computing. In this talk, I will discuss key considerations for the neuromorphic computing to be realized in a commercial system and strategies to occupy a position with a stably growing market share.

In-memory neural network accelerators have been garnering interest as an energy and area-efficient platform for lightweight applications. We, however, still do not see a successful commercial example based on the concept due to several technical challenges: accuracy degradation due to the analog noise, large overhead in peripheral circuits such as analog-todigital converters (ADCs), and limited capability to demonstrate large-scale in-memory accelerator chips based on exploratory devices, to name a few. In this talk, I will briefly introduce the algorithm/hardware co-design techniques that my group has been developing to address the issues. I would also like to discuss the research direction for large-scale in-memory accelerators based on emerging device technologies, given the limitations in the maturity of the technologies.

Non-volatile memory (NVM)-based processing-in-memory (PIM) architectures have paved the way for energy-efficient AI systems owing to high cell density, non-volatility, and compatibility with a CMOS process. While NVM as a synapse device has struggled to tackle the trade-off between ideal characteristics such as appropriate ON/OFF ratio for multi-bit encoding, low ON/OFF current, and retention, it does not always match with the desirable features in designing PIM architectures. In addition, the variations in NVM devices make the device a black box, thereby hindering the optimized design in peripherals for energy efficiency. In this talk, I will briefly introduce the on-chip RRAM-based PIM architecture fabricated in an integrated CMOSRRAM process and the difficulties in designing a PIM architecture with black boxes. Then, I would like to discuss the feasibility of on-chip NVM-based PIM architectures in academia and the desirable research direction of NVMbased PIM architectures at the circuit and device sides. In addition, functional completeness in NVM-based PIM architectures will also be discussed, considering the practical AI applications.

In-memory computing has been drawing significant attention as a promising candidate for energy-efficient AI acceleration circuit topology. However, its commercial product adoption has not been realized yet and fundamental limits with inaccurate, variation-sensitive and non-deterministic devices and circuits must be addressed for industry-wide adoption. In this talk, a few of recently explored circuit designs for addressing these challenges will be introduced. Circuit designs with better linearity and more tolerance to PVT variations for both SRAM-based and RRAM-based in-memory computing macro will be discussed. Potential next research directions, will be also briefly discussed.

The dataflow of an accelerator SoC has a great impact on the performance and energy efficiency. Thus, it is of significant importance to simulate and optimize a dataflow early in the design, e.g., without going through RTL coding. SystemC-TLM based virtual platform is considered as one of the most promising techniques, which helps us to explore a broad design space of algorithms and architectures a few orders of magnitude faster than the conventional RTL models. In this talk, a virtual platform is proposed to design and optimize a neural network hardware accelerator. The proposed virtual platform can model not only the dataflow inside the accelerator but also the dataflow outside the accelerator in a cycle-accurate manner. The focus of this talk is on the memory-centric neural network SoCs such as DRAM connected accelerators and eFlash-based compute-in-memory (CiM) accelerators. The technical issues related to virtual platform simulation based design optimizations will be discussed in this talk.

A human brain contains 86 billion neurons and consumes 20 Watts while performing extremely complex cognitive tasks at very good accuracy. This combination of extreme accuracy and efficiency has motivated the computer engineering communities to build a processor that mimics a biological brain with the vision of achieving similar accuracy and efficiency. Toward this vision of neuromorphic computing, our team also made significant efforts, prototyping multiple SNN processors. One of the earlier SNN processor chips that we developed features fully spike-driven neurons and synapses. It consumes only 300 nW, marking 104X reduction over the previous SNN hardware. Also, the processor achieves the per-neuron power consumption of 460pW, which for the first time approaches to the level of biological power efficiency (230pW). Also, more recently, we developed another SNN processor that features more biologically-plausible neurons and recurrent as well as feedforward connections. We also integrated emerging SRAM-based digital in-memory-computing (IMC) hardware to leverage its massive energy efficiency and throughput in performing synapse operations. Executing the automatic speech recognition (ASR) task, this SNN processor improves the power efficiency by 50X over the state-of-the-art ASR hardware at the same accuracy. Despite these exciting results, we are still far away from our ultimate goal. In the second half of the presentation, we will summarize the challenges we see in neuromorphic processor design and propose potential directions to the breakthrough.